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NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition
https://doi.org/10.20736/0000001207
https://doi.org/10.20736/00000012074ebfd0f5-860f-49d3-8e6a-6c33ae722180
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition (380.6 kB)
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| アイテムタイプ | レポート / Report(1) | |||||||||||
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| 公開日 | 2006-02-16 | |||||||||||
| タイトル | ||||||||||||
| タイトル | NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition | |||||||||||
| 言語 | en | |||||||||||
| 言語 | ||||||||||||
| 言語 | eng | |||||||||||
| キーワード | ||||||||||||
| 言語 | ja | |||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | テクニカルレポート | |||||||||||
| キーワード | ||||||||||||
| 言語 | en | |||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Technical Report | |||||||||||
| 資源タイプ | ||||||||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||||||||
| タイプ | departmental bulletin paper | |||||||||||
| ID登録 | ||||||||||||
| ID登録 | 10.20736/0000001207 | |||||||||||
| ID登録タイプ | JaLC | |||||||||||
| 著者 |
米田, 友洋
× 米田, 友洋
× Myers, Chris
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| 抄録 | ||||||||||||
| 内容記述タイプ | Abstract | |||||||||||
| 内容記述 | This paper presents a decomposition based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed STG to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas(Nii-Utah Timed Asynchronous circuit Synthesis system), and its very first version is available at http://research.nii.ac.jp/~yoneda. | |||||||||||
| 言語 | en | |||||||||||
| 書誌情報 |
ja : NIIテクニカル・レポート en : NII Technical Report p. 1-16, 発行日 2006-02-16 |
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| 出版者 | ||||||||||||
| 出版者 | 国立情報学研究所 | |||||||||||
| 言語 | ja | |||||||||||
| ISSN | ||||||||||||
| 収録物識別子タイプ | ISSN | |||||||||||
| 収録物識別子 | 1346-5597 | |||||||||||
