{"created":"2021-03-01T05:52:55.848713+00:00","id":1207,"links":{},"metadata":{"_buckets":{"deposit":"bcf9a5c2-9675-414e-b03f-b3ba668ec6e2"},"_deposit":{"id":"1207","owners":[],"pid":{"revision_id":0,"type":"depid","value":"1207"},"status":"published"},"_oai":{"id":"oai:repository.nii.ac.jp:00001207","sets":["136"]},"author_link":[],"control_number":"1207","item_5_biblio_info_30":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-02-16","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"16","bibliographicPageStart":"1","bibliographic_titles":[{"bibliographic_title":"NIIテクニカル・レポート","bibliographic_titleLang":"ja"},{"bibliographic_title":"NII Technical Report","bibliographic_titleLang":"en"}]}]},"item_5_description_28":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This paper presents a decomposition based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed STG to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas(Nii-Utah Timed Asynchronous circuit Synthesis system), and its very first version is available at http://research.nii.ac.jp/~yoneda.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_5_identifier_registration":{"attribute_name":"ID登録","attribute_value_mlt":[{"subitem_identifier_reg_text":"10.20736/0000001207","subitem_identifier_reg_type":"JaLC"}]},"item_5_publisher_31":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"国立情報学研究所","subitem_publisher_language":"ja"}]},"item_5_source_id_32":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1346-5597","subitem_source_identifier_type":"ISSN"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"米田, 友洋","creatorNameLang":"ja"},{"creatorName":"Yoneda, Tomohiro","creatorNameLang":"en"}]},{"creatorNames":[{"creatorName":"Myers, Chris","creatorNameLang":"en"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2019-03-11"}],"displaytype":"detail","filename":"06-001E.pdf","filesize":[{"value":"380.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition","url":"https://repository.nii.ac.jp/record/1207/files/06-001E.pdf"},"version_id":"38fe9ce4-503f-4c48-9a92-db449e9e00fe"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"テクニカルレポート","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"Technical Report","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition","subitem_title_language":"en"}]},"item_type_id":"5","owner":"1","path":["136"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2006-02-16"},"publish_date":"2006-02-16","publish_status":"0","recid":"1207","relation_version_is_last":true,"title":["NII Technical Report (NII-2006-001E)：Synthesis of Timed Circuits based on Decomposition"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2022-12-28T04:35:32.105909+00:00"}